In a memory system where a memory controller controls multiple memory devices, interface devices are often deployed to improve the quality of the signal transmissions between the memory controller and the memory devices. As an example, DDR2 and DDR3 Registered memory modules use one or more registers to buffer and re-drive the command, control and address signals from the host memory controller to multiple DDR2 and DDR3 SDRAM devices. As a second example, DDR3 Load-Reducing Memory Modules (LRDIMM) use a memory buffer to re-drive the command, control, address and data signals from the host memory controller to and from multiple DDR3 SDRAM devices.
Memory interface devices can be used to isolate or segment portions of the memory system from each other, improving the quality of signal transmission as well as potentially reducing the power consumption of the memory system and improving the reliability characteristics of the memory system.
High-speed digital signals, such as the data, clock and control signals that are conveyed between a host controller and a memory module, are typically received by a respective receiver circuits. Each signal is also typically terminated, usually to the junction point of a voltage divider. However, this arrangement can be inefficient, as current is always being conducted (bled) by one branch or the other of the divider.
From the above, it is seen that techniques for improving memory module devices and methods of use are highly desirable.